The present invention is related to semiconductor integrated circuit process technology, and more particularly, to a method of verifying a sub-resolution assist feature design to enhance the resolution of a photomask and improve the robustness of the lithography process in a semiconductor fabrication process.
Photolithography is routinely used to define patterns in semiconductor integrated circuits. As the minimum feature size of the integrated circuits continues to shrink, there are significant decreases in the lithography process window to generate minimum feature lines. Various resolution enhancement techniques have been generated in the past to improve the process stability when designing features at minimum dimensions. Sub-resolution assist features (SRAFs), also known as scattering bars, are used to facilitate the printing of semi-dense and isolated lines by increasing the optical density near the features to be imaged. Sub-resolution assist features are added to the photomask layout to facilitate the printing of the main features without resolving the assist features during silicon imaging. The aforementioned SRAFs are one of the evolving resolution enhancement techniques currently used for lithography having a low end process scaling factor (commonly referred to as k1 factor). The presence of sub-resolution assist features boosts the depth of focus, especially for small isolated design features.
The initial concept of using SRAFs to enhance the lithographic process robustness is described in U.S. Pat. No. 5,447,810 to Chen et al. The sub-resolution assist features provide increased depth of focus and minimize CD (critical dimension) differences between selected features. More particularly, Chen et al. show the benefit of assist features through contacts when used in conjunction with quadruple illumination. However, Chen at al. are only concerned with the placement of very simple assist features, limiting themselves to using one assist feature per isolated edge. Moreover, no reference is made on how to systematize the design and optimally place features.
Lately, there has been significant development work to adapt the initial concept to a full manufacturing solution. One of the main advancements is to develop a so-called sub-resolution assist feature design strategy. In an article by Scott M. Mansfield et al. “Lithographic comparison of assist feature design strategies” published in the Proceedings of SPIE—International Society for Optical Engineering (USA) Vol. 4000, pp. 63–76, there are described design strategies for sub-resolution assist features by using multiple SRAFs (the number of sub-resolution assist features varying from one to four assist feature per space). Mansfield et al. describe the theory and experimental results to optimize: 1) the proper assist feature width applicable to lithographic tooling and illumination condition, 2) the distance from the assist to the main design detail, and 3) the number of assist features to be used for each space. Mansfield et al. further discuss the photomask fabrication and various inspection limitations in the presence of sub-resolution assist features, and examine the sensitivity of the photomask layout to the lithographic tool components and settings. The above method, when applied to the SRAF design strategy, provides accurate rules to place assist feature in a one-dimensional environment for a plurality of design pitches. However, it does not include algorithms or computer programs to automatically place SRAF in the photomask layout of an integrated circuit (IC) chip design. In order to apply the SRAF design strategy to a full IC chip design, the complexity of the layout needs to be fully anticipated and the heuristics for the placement of the assist feature need to be developed.
Implementing the SRAF design strategy into a complex real chip design by developing automated software tools/algorithms is described in U.S. Pat. No. 6,413,683 to Liebmann et al. Therein, a method is provided for placing SRAFs in a photomask layout by considering details of the electrical circuit, in order to establish priorities for placing SRAFs and resolve conflicts during the placement thereof.
The proficiency of the assist feature software tools is sometimes limited by the complexity of the two-dimensional layout and by the mask layout inspection limit induced clean up. Depending on the individual design style, a semiconductor circuit can be represented by various layout configurations that obey design rules. As the design style changes from the electrical circuit functionality and individual design practices, the software algorithms that work on one design may fail on another. Oftentimes, to maintain the generality of the software, the cleanup that is required to remove the SRAFs may introduce mask and process issues that are overly aggressive. Inadequate removal of assist features can be detrimental to the main design features, (which will be explained hereinafter in more detail). The above mentioned imperfections are caused by a prioritization that occurs during placement and by a cleanup that relies on empirical rules or which is bound by a limited experience of the properties of the assist features rather than by an accurate description of what is needed for a given layout situation. The assist feature placement rules are generally derived from a one-dimensional environment. When converted to a two-dimensional product layout, the placement algorithm interprets the assist feature placement rules, leaving the prioritizing and placement become dependent on empirical experience. By way of example, “L”shaped assist features may be removed because under certain layout situations, the “L”shaped assist features are printed in silicon resist image. However, not all “L”shape assist features print in silicon image. If they do not print and are instead removed, the main feature may, as a result, suffer CD variations in the absence of the assist feature. Generic style options available in current SRAF generation algorithm do not consider the rich variation of details typical of a true layout, and therefore they fail to provide the best possible placement strategy tailored to a particular layout situation.